Computer controlled high-speed circuit for testing electronic devices

ABSTRACT

High-speed testing circuitry which, when coupled to one terminal of a multi-terminal electronic device, such as an integrated circuit, can either supply test stimuli signals up to a frequency of 30 MHz, receive output signals produced by the device under test in response to test stimuli signals applied by associated test circuits and compare these signals against computer predicted signals, or provide for parametric testing of the device. .Iadd.

BACKGROUND OF THE INVENTION

1. Field of the Invention .Iaddend.

This invention is for high-speed testing circuitry particularly usefulfor the production testing of high-speed electronic devices. .Iadd.

Description of the Prior Art .Iaddend.

.[.It is similar to, but an improvement over that invention describedand claimed in.]. U.S. Pat. No. 3,976,940, which was assigned to theassignee of the present invention.[.. This prior art patent.]..Iadd.,.Iaddend.describes a computer-controlled testing circuit containinghigh-speed switching circuitry that applies two predetermined referencevoltage levels, representing the two binary states, to an input terminalof an electronic device under test (DUT). When the testing circuit isconnected to an output terminal of the DUT, the test stimuli signalsproduced by another identical testing circuit will produce two-leveloutput signals from the DUT that are compared in the testing circuitrywith signals predicted by the associated computer to detect functionalerrors.

This prior art test circuit materially advanced the state of theexisting art by increasing the then upper limit testing frequency fromapproximately 5 MHz to a greatly improved 10 MHz.

.[.The circuitry of the present invention is a further improvement andis capable of functionally testing electronic devices at a rate of 30MHz, as will be shown in greater detail hereinbelow..].

BRIEF SUMMARY OF THE INVENTION

The high-speed testing circuit of the invention may be operated in anyone of three modes. In its parametric testing mode, it merely providesan interconnection between the associated test system computer and oneterminal of the device under test (DUT). In the stimulation mode, thehigh-speed test circuit may be connected to an input terminal of a DUTto provide input signals at any two of four voltage reference levelsrepresenting the two binary states, which signals are switched to andfrom those two states at signal frequencies up to 30 MHz withoutswitching transients by a novel dual bridge drive circuit.

In its signal-receiving mode, the output signals from the .[.device.]..Iadd.DUT.Iaddend., now being driven by input signals from another testcircuit in its stimulation mode, are applied to a comparator whichcompares these signals with reference signals predicted and supplied bythe associated test system computer.

A separate skew adjusting circuit having both coarse and fineadjustments is included in the stimulation circuitry for adjusting bothlead and lag edges of the signal to align with the edges of test stimulisignals supplied by other associated testing circuits. A similar dualskew adjustment circuit is provided at the output of the comparator tocompensate for the various propagation delays and to align the edges ofthe pulses from the comparator with those of other associated testcircuits.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings which illustrate the preferred embodiment of theinvention:

FIG. 1 is an overall block diagram of a circuit testing system whichincludes the testing circuit of the present invention;

FIG. 2 is a schematic diagram of the analog reference supply and skewadjusting circuits of FIG. 1;

FIG. 3 is a schematic diagram illustrating the drive circuit and theinput-output select circuit of FIG. 1; and

FIG. 4 is a logic diagram of the comparator and the comparator skewadjustment circuit of FIG. 1.

DETAILED DESCRIPTION

Turning now to a detailed description of the invention, FIG. 1 is anoverall block diagram illustrating the testing circuit 10 coupledbetween a test system computer 12 and a device under test (DUT) 14. Inpractice, one test circuit 10 is coupled to each terminal of themulti-terminal DUT 14 and is capable of being operated by the computer12 in any one of three modes, depending upon whether the circuit 10 iscoupled to a DUT input signal terminal, output signal terminal, or othervarious function or supply terminals. Thus, a DUT 14 having, forexample, sixteen terminals or pins, would be tested in a fixturecontaining sixteen identical testing circuits 10 controlled by a singletest system computer 12.

If, for example, the testing circuit 10 of FIG. 1 is coupled to a signalinput terminal of DUT 14, the computer 12 which contains a storedprogram specifically written to test the particular DUT, will firstclose relay contact K1 to connect the test stimuli section of thecircuit 10 to the DUT 14. This section includes an analog referencesupply 16 which, in response to the program from computer 12, producestwo levels of D.C. reference voltages designated VR0 and VR1, the lowand high voltage levels of the pulse pattern to be applied to the DUT14. The selected VR0 and VR1 voltage levels are applied to a drivercircuit 18 which switches between the two voltage levels to produce apattern of pulses in accordance with the data input or F input generatedwithin the computer and transmitted by way of the data input line 20 toa skew adjusting circuit 22 which may be manually adjusted to align theleading and the lagging edges of the input signal to conform withleading and lagging edges of other associated circuits coupled to theDUT 14 and being operated in the test stimuli mode. The computer 12 alsoapplies to the circuit 10 an input-output select signal which activatesthe I/O select circuit 24 which opens or closes a high-speed gate in thedriver circuit 18 to either stop or admit the flow of data pulses intothe DUT 14.

The circuit test system is also capable of performing parametric testson the DUT 14. A parametric (or D.C.) test allows a voltage or currentto be measured on any input or output pin of the DUT, while forcing acurrent or voltage simultaneously. This type of testing is performed bya precision measurement unit (PMU) 26 located within the test systemcomputer 12. Parametric testing is essential for defining minimumparameters for semiconductor devices (as well as other types ofcircuits), such as saturation voltage, input leakage current, etc. Whenbeing operated in this mode, the computer 12 closes only the relaycontact K2 so that the DUT 14 is coupled into the PMU unit 26 of thecomputer 12 via the conductor 28.

When the testing circuit 10 is coupled to a signal output terminal ofthe DUT 14, the computer 12 closes only relay contact K3 so that the DUToutput signals that are generated in response to test stimuli signalsfrom other testing circuits driven by the computer 12 will be applieddirectly to a comparator 30, which also receives the predicted signalsfrom the computer 12 via the input line 32. In addition, a data inputsignal from the stimuli section of the circuit 10 is transmitted througha delay line 34 to the comparator .[.40.]. .Iadd.30.Iaddend.. The delayin the delay line 34 is calculated to be substantially equal to thepropagation losses through the driver circuit 18 and portions of thecomparator circuit 30 and the delayed signals are used to switch theoutput signals of the comparator in accordance with the input dataapplied to the DUT 14. At the output of the comparator 30 is a skewadjusting circuit 36 which is identical with and similar in operation tothe circuit 22. The output of the skew adjusting circuit 36 is appliedback into the test system computer 12 which registers either acceptanceor rejection of the DUT 14.

FIG. 2 illustrates in better detail the analog reference supply 16 andskew adjustment circuit 22 of FIG. 1.

The function of the analog reference supply 16 is to provide a pair ofD.C. output signals, VR0 and VR1, representing the two binary voltagelevels of the pulse train that will be applied to the device under test.DUT 14 may contain TTL, ECL, or FET circuitry, each of which must betested with pulses having various voltage levels. Therefore, thereference supply 16 must be capable of providing those levels asdictated by the program of the computer 12. The actual voltage levelsare produced by the test system computer and two pairs of high and lowreference voltages are introduced to the input terminals of a multiplexswitch circuit 40 shown by dashed lines within the analog referencesupply 16 of FIG. 2. Thus, two different voltage level signalsrepresenting the reference voltages VR1 and two representing VR0 areapplied from the computer to the input terminals 42, 43 and 44 and 45,respectively. The selection of the appropriate VR1 and VR0 signal ismade by the computer by applying an excitation signal to the inputterminals 46 and 48. Therefore, appropriate excitation of the multiplexcircuit 40 by the system test computer 12 will produce output voltagelevels from the multiplex switch 40 that are of a constant level and arewithout switching transients or glitches that are inherent during normalvoltage switching operations. In operation, therefore, while themultiplex switch 40 is connected to output one pair of voltage levels,the test computer will apply the next voltage levels to be used in thetest, thus providing a settling time and a resulting elimination ofswitching glitches.

The selected voltage levels VR0 and VR1 are applied to the referencesupply circuitry 50 and 52. In FIG. 2, the circuitry 52 is shown as anamplifier and is identical with the circuitry 50 which is illustrated indetail within the dashed section in the analog reference supply 16 ofFIG. 2. Thus, the following description of the circuitry 50 is intendedto also apply to the circuitry 52.

One output of the multiplexing switch 40 is applied through a 10Kresistor 54 to the non-inverting input terminal of a fast unity gainoperational amplifier 56 coupled between a +12 volt and a -10 volt powersource. The output of amplifier 56 drives a voltage following currentbuffer circuit capable of generating an output of approximately 20 ma.at the same voltage level as that applied to the reference supply 16 bythe system computer 12. In the embodiment illustrated, the currentbuffer includes a balanced circuit containing an NPN transistor 58 inseries with a PNP transistor 60. The collector of transistor 58 iscoupled through suitable resistance to the positive 12-volt source andthe collector of the transistor 60 is coupled through an identicalresistor to the negative 10-volt source. The emitters of transistors 58and 60 are connected together through a pair of matched resistors in apush-pull configuration, the interconnection point of which is coupledto the output line of the reference supply circuitry 50.

The base of transistor 58 is coupled to the positive voltage sourcethrough a resistor 62 and to the output terminal of the amplifier 56through a forward biased diode 64. Similarly, the base of transistor 60is connected to the negative voltage source through a resistor 66 whichis identical in value to resistor 62, and is also connected to thecathode of a diode 68, the anode of which is coupled to the output ofthe amplifier 56. The output of amplifier 56 is coupled through acapacitor 70 to the output line of the circuit 50, and the output lineof circuit 50 is also coupled to provide feed-back to the invertingterminal of the amplifier 56. Thus, the voltage level applied to themultiplexing switch from the system computer is duplicated by theamplifier 56, the output of which controls the gating of the transistors58 and 60 so that the circuit output line, which is centered between theemitters of the two transistors 58 and 60, will be at an identicalpotential level, VR1.

Similarly, the circuitry 52 provides a VR0 signal at a level dictated bythe system computer. Both the VR0 and the VR1 voltage levels are thenapplied to the driver circuit 18 which, in effect, operates as asingle-pole double-throw switch that is toggled at a rate of up to 30MHz by the data input, hereafter designated F, from the test systemcomputer 12.

It will be appreciated that many devices to be tested by the testingcircuitry of the invention may require several simultaneous test stimulisignals from other testing circuits incorporated in the circuit testingsystem and that it is essential that adjusting means are provided forassuring that all test stimuli signals are properly timed so that allleading and trailing edges of all test stimuli signals applied to theDUT 14 are in proper correspondence and alignment. Therefore, the Fsignals provided by the system computer 12 are applied to a skewadjustment circuit 22, such as that shown in detail within the dashedline 22 of FIG. 2. The skew circuit illustrated in FIG. 2 is similar tothat described and claimed in the aforesaid U.S. Pat. No. 3,976,940,except that the improved skew adjustment circuit of the presentinvention has both coarse and fine skew adjustment provisions, whereas,the aforementioned patent describes only a fine skew adjustment means.The skew adjustment circuit permits independent adjustment of theleading and trailing edge delay of F data as it propagates from theinput lines from the system computer 12 to the DUT 14.

The F input data signals from the system computer 12 are coupled to thenon-inverting and the inverting inputs of an amplifier 72 which, becauseof the very high speeds involved, is preferably a high-speeddifferential amplifier often referred to as a line receiver. Theinverting output terminal of amplifier 72 is coupled to a -5.2 voltsupply through a variable resistor 75 and the non-inverting output ofthe amplifier is coupled to the negative source through an identicalvariable resistor 76. Varying of the resistor 74 will advance or delaythe trailing edge of the F data and varying the value of resistor 76will advance or delay the leading edge of the F data.

The non-inverting output of amplifier 72 is connected to thenon-inverting input of a similar amplifier 78 through series resistors80 and 82, the junction of which is connected through a small capacitor84 to ground reference. Similarly, the inverting output of amplifier 72is coupled to the inverting input of amplifier 78 through seriesresistors 86 and 88, the interconnection of which is coupled to groundthrough a small capacitor 89.

The inverting output of the amplifier 78 is connected directly to oneterminal of a single-pole double-throw switch 90, while thenon-inverting output of the amplifier 78 is connected through a NOR-gate91 to the second terminal of the single-pole double-throw switch 90.NOR-gate 91 is preferably a high-speed ECL circuit that will provide apropagation delay of between one and one-half and two nanoseconds and,when incorporated into the circuit by switch 90, provides a coarseadjustment to the skew adjustment circuit 22. Thus, adjustment of thepotentiometers 74 and 76 will provide a smooth and fine adjustment ofapproximately two nanoseconds to the leading and trailing edges of the Fdata signal, while the addition of the NOR-gate 91 of the circuit willadd an additional step adjustment of approximately two nanoseconds.

The output of the skew adjustment circuit is applied to the input of anOR/NOR gate 92, the output signals of which are then applied to anamplifier 93, the output of amplifier 93 being applied to the drivercircuit 18, as illustrated in FIG. 2. The skew adjusted F data signalsare also sampled at the output of the OR/NOR gate 92 and applied throughan amplifier 94 to a time delay circuit 34, the output of which isapplied to the comparator circuit 30, as will be subsequently described.

FIG. 3 includes detailed schematic diagrams of the driver circuit 18 andthe input/output select circuit 24, as previously mentioned inconnection with FIG. 1. As shown in FIG. 3, the F data signals producedat the output of the skew adjustment circuit 22 of FIG. 2, is applied tothe F and .[.F.]. .Iadd.F .Iaddend.input terminals, and the two voltagelevel signals produced by the analog reference supply 16 of FIG. 2 areapplied to the VR0 and VR1 input terminals of the driver circuit 18 ofFIG. 3.

The driver circuit 18 includes two diode bridge circuits 98 and 100operated as high-speed switches. The interconnected diode anodes in thebridge 98 are connected to the collector of a PNP transistor 102 and theinterconnected anodes in the bridge 100 are connected to the collectorof an identical PNP transistor 104. The emitters of transistors 102 and104 are connected together through balanced series resistors, theinterconnecting point of which is connected to the collector of a PNPtransistor 106, the emitter of which is connected through a low valueresistor to V_(CC), a source of positive voltage, the interconnecteddiode cathodes in the bridge 98 are connected to the collector of NPNtransistor 108 and the interconnected cathodes in the diode bridge 100are connected to the collector of an identical NPN transistor 110. Theemitters of transistors 108 and 110 are connected together throughbalanced series resistors and to the collector of NPN transistor 112,the emitter of which is connected to the -V_(EE) supply through asuitable resistor to provide a constant current source for thedifferential pair. One side of the diode bridge 98 is connected to theVR0 input terminal and the corresponding input of the diode bridge 100is connected to the VR1 input terminal. Characteristics of bridgenetworks of the type described herein are that the bridge isself-balancing, it is self-compensating as a function of temperature,and has the ability to operate as a floating network. Thus, if currentis permitted to flow through one diode bridge, such as a current flowthrough transistor 102, diode bridge 98, and transistor 108, a voltagelevel applied to the VR0 input corner of the bridge will be duplicatedat the opposite corner and to the output line 114. Thus, the terminalsof bridges 98 and 100 that are symmetrically opposite the terminals towhich are applied the VR0 and VR1 signal levels, are connected togetherand to the output line 114 of the bridge switching circuit.

The bridges 98 and 100 are actuated by a current flow through theirassociated transistor switches. Thus, when transistors 102 and 108 areconductive, current will flow through the bridge 98 and a voltage willbe produced on the output line that precisely corresponds to the voltagelevel applied to VR0 input terminal. Conversely, switching to the highpulse level will switch off transistors 102 and 108 and will rendertransistors 104 and 110 conductive to permit a flow of current throughthe bridge 100 and so that the VR1 voltage applied to the bridge will betranslated to the output line 114.

It will be appreciated that the two F data input signals were adjustedand amplified in high-speed ECL circuit components which typicallyproduced a high level output voltage of approximately -0.8 volts and alow level output voltage of approximately -1.7 volts. Since these ECLlevel swings must drive switching transistors in the drive circuit 18,it is first necessary to apply these signals to a signal translatorwhich will convert the levels to those suitable for the switchingoperations. Therefore, the F input terminal of the drive circuit 18 isconnected to the anode of a Zener diode 116 and the .[.F.]. .Iadd.F.Iaddend.input terminal is connected to the anode of a Zener diode 118.Zener diodes 116 and 118 are carefully matched, each having a Zenervoltage of preferably 8.2 volts. The cathode of Zener diode 116 isconnected through a resistor 120 to the +12 volt V_(CC) supply and thecathode of Zener diode 118 is coupled through an identical resistor 122to the positive supply. The anode of Zener diode 116 is connected to theanode of a .[.diode.]. .Iadd.pair of similar diodes .Iaddend.124 .[.,the cathode of which is.]. connected in series .[.with a similardiode.]. and through a resistor 126 to a -10 volt supply. Similarly, theanode of Zener diode 118 is coupled through two diodes in series 128 andthrough resistor 130 to the negative supply. .Iadd.Resistors 120 and 126are substantially identical to resistors 122 and 130, respectively..Iaddend.The cathode of Zener diode 116 is also coupled through aresistor to the base of PNP transistor 102 and the cathode of Zenerdiode 118 is coupled through a similar resistor to the base of PNPtransistor 104. The base of NPN transistor 110 is coupled through aresistor to the point interconnecting the resistor 126 with the seriesdiodes 125 and the base of NPN transistor 108 is coupled through anidentical resistor to the junction of resistor 130 and the diode pair128.

The matched Zener diodes 116 and 118, together with their associatedseries resistors, form the signal translator that translates the ECLlevels applied to the F and .[.F.]. .Iadd.F .Iaddend.input terminalsinto voltage levels suitable for switching the transistors 102, 104, 108and 110. An example of the operation of the signal translator is asfollows: Assume a high level ECL input is applied to the input terminalsso that the voltage level appearing at the F terminal may be -0.8 and atthe .[.F.]. .Iadd.F .Iaddend.terminal, -1.7. There is a normal currentflow through each signal translator circuit between the +12 volt and -10volt supplies and there is a constant 8.2 volt drop across each Zener116 and 118. Therefore, a -0.8 volt signal appearing on the anode of theZener diode 116 will be translated to a +7.4 volt level at the cathodeof Zener diode 116. Similarly, a -1.7 volt applied to the anode of Zenerdiode 118 will be raised to the level of +6.5 volts at the cathode. Inthe example, a potential of 7.4 volts is now applied to the base of.[.NPN.]. .Iadd.PNP .Iaddend.transistor 102 and 6.5 volts is applied tothe base of .[.NPN transistor 102 and 6.5 volts is applied to the baseof NPN.]. .Iadd.PNP .Iaddend.transistor 104, thereby turning ontransistor 104 and turning off transistor 102.

Two pairs of series diodes 124 and 128 provide a 1.2 volt drop belowthat applied to the input terminals. Thus, in the example of theoperation of the circuit, the -0.8 volt signal at the F terminal willdrop to -2 volts across the diodes 124 and this level will be applied tothe base of the NPN transistor 110. The -1.7 volts applied to the.[.F.]. .Iadd.F .Iaddend.input terminal will similarly be lowered to.[.-3.9.]. .Iadd.2.9 .Iaddend.volts at the base of NPN transistor 108.Thus, transistor 108 will be turned off and transistor 110 will turn on.The flow of current through the constant current source transistor 106,switching transistor 104, bridge 100, transistor 110 and the constantcurrent source transistor 112 will therefore enable the bridge 100 sothat the VR1 signal applied to the bridge will be repeated as VR1 on theoutput line 114.

When the data input is switched, the F input, previously at -0.8 volts,will drop to -1.7 volts and the .[.F.]. .Iadd.F .Iaddend.input willswitch from the -1.7 volts to -0.8 volts. The translator diodes having aZener voltage of 8.2 volts will then translate these data input signalsso that the .[.F.]. .Iadd.F .Iaddend.input of .Iadd.-.Iaddend.0.8 voltswill apply +7.4 volts to the base of transistor .[.102.]. .Iadd.104.Iaddend.and the F input of -1.7 volts will be translated to +6.5 voltsand applied to the base of transistor .[.104.]. .Iadd.102.Iaddend..Thus, transistor 102 will turn on and transistor 104 will turn off.Similarly, the two pairs of diodes 124 and 128 will further drop thedata input voltage levels by 1.2 volts to apply -2.0 volts to the baseof NPN transistor .[.110.]. .Iadd.108 .Iaddend.and .[.-3.9.]. .Iadd.-2.9.Iaddend.volts to the base of transistor .[.108.]. .Iadd.110.Iaddend.thereby turning on transistor 108 and turning off transistor110. Current now no longer flows through the branch containing diodebridge 100 and the VR1 voltage level applied to the bridge 100 is nottranslated to the output line. Instead, bridge 98 is conducting and theVR0 level applied to that bridge now is repeated on line 114. As theinput data is switched on the F and .[.F.]. .Iadd.F .Iaddend.inputterminals, the current flow through the bridges 98 and 100 will besimilarly switched and are capable of being switched at extremely highspeeds to produce a train of output pulses that will provide teststimuli signals of up to 30 MHz to the DUT 14.

The output of the bridge switching circuit in the driver circuit 18 isapplied via output conductor 114 and through an output impedancematching potentiometer 131 to the interconnected source terminals of twoparallel connected double-diffused N-channel enhancement-type fieldeffect DMOS transistors 132 and 134 which are operated as extremelyhigh-speed switches to switch the data signal on or off to the DUT 14.Therefore, the drain terminals of DMOS transistors 132 and 134 arecoupled together and to one contact of the switch K1, and the gateterminals of the DMOS transistors are coupled together for control bythe input-output select circuit 24.

The input-output select circuit 24 is controlled by the test systemcomputer 12 which applies signals to the input terminals 136 and 138 ofthe circuit 24. Terminal 136 is coupled to the non-inverting inputterminal of an amplifier 140 which, because of the high switching speedrequirement, should be an ECL circuit, such as the type often designatedas a line receiver. Similarly, the terminal 138 is applied to theinverting input terminal of the amplifier 140. Because the outputsignals from the amplifier 140 are at the ECL levels and not suitablefor the control of the following transistor circuit, the output signalsare applied through a signal translator similar to that described inconnection with the driver circuit 18. Therefore, the non-invertingoutput of amplifier 140 is applied through a Zener diode 142 to the baseof NPN transistor 144 and the inverting output of amplifier 140 isapplied through an identical matched Zener diode 146 to the base of NPNtransistor 148. The base of transistor 148 is coupled to the -10 voltsupply through a resistor 150 and the base of transisor 144 is coupledto the negative supply through an identical resistance 152. The emittersof transistors 144 and 148 are connected together and to the negativesupply through a resistor 154 which forms a constant current source forthe differential transistor pair 144 and .[.150.]. .Iadd.148.Iaddend..The collector of transistor 148 is connected to a +18 volt supplythrough a series-connected resistor 158 and choke 156 which functions tospeed up the driving signals to the gates of the DMOS transistors 132and 134. The collector of transistor 148 is also connected to theinterconnected gate terminals of the DMOS switching transistors 132 and134. The collector of transistor 144 is connected to the anode of a 16volt Zener diode 160, the cathode of which is coupled to the +18 voltsupply. The purpose of the Zener diode 160 is to balance the ON/OFFcurrent through transistors 144 and 148. When transistor 144 isconducting, current flows from the +18 volt supply to the -10 voltsupply through Zener diode 160, transistor 144 and resistor 154. Whentransistor 144 is suddenly switched off and transistor 148 is switchedon, the same amount of current will flow through resistance 158, choke156, transistor 148 and the 100-ohm .[.resistance.]. .Iadd.resistor154.Iaddend.. Thus, there is no current change between on and off state,and voltage spikes due to current changes will be materially reduced.

In operation, when a high signal is applied to the input terminal 136, acorresponding high signal will be produced at the non-inverting outputof amplifier 140 and will be applied to the base of transistor 144 torender that transistor conductive. Simultaneously, with the switching onof transistor 144, transistor 148 is switched off, thus applying a highvoltage to the collector of transistor 148 and the interconnected gateterminals of the switching transistors 132 and 134, thereby renderingthose transistors conductive. When the input signals to terminals 136and 138 are switched to their opposite state, the higher level signalnow on terminal 138 will be applied through amplifier 140 and across thesignal translator Zener diode 146 to apply the higher level signal tothe base of transistor 148. Transistor 148 is thereby turned on andtransistor 144 is turned off. The collector of the conducting transistor148 is now at a negative potential and this level is applied to thegates of the DMOS transistors 132 and 134 to render them non-conductive,thus opening the input-output switch to the DUT 14.

FIG. 4 contains a detailed block diagram of the comparator 30 of FIG. 1and a schematic diagram of the associated skew adjustment circuit 36.

The comparator 30 receives input signals from the system computer 12 andapplies them to the multiplexing switch 162 which is identical with themultiplexing switch 40 previously described in connection with theanalog reference supply 16 of FIG. 2. The computer introduces D.C.signal levels representing two high and two low voltage levels to inputterminals 164 and 166, respectively, and level-selecting signals toinput terminals 168. The two output levels from the multiplexing switch162 are applied to the inverting inputs of comparators 170 and 172,while input signals from the DUT 14 are transmitted through the switchK3 to both of the non-inverting input terminals of the comparators 170and 172. Comparators 170 and 172 are readily available on the commercialmarket, and one such comparator that is suitable for use in thecomparator circuit is the type Am687 manufactured by Advanced MicroDevices of Sunnyvale, California.

The outputs of the comparators 170 and 172 are applied to the inputterminals of amplifiers 174 and 176, respectively, and the output ofthese amplifiers are applied to the input terminals of a multiplexer,shown within the dashed line 178. The multiplexer 178 is also acommercially available item and may, for example, be a Motorola MECL10134 multiplexer with latch. Multiplexer 178 receives an additionalinput from the delay circuit 34 of FIGS. 1 and 2, which samples the Fdata signals and delays them by an amount equal to the propagationdelays in the testing circuit. The multiplexer 178 then switches betweenthe output levels of amplifier 174 and 176 at a rate controlled by thedelayed F data. The output of the comparator 30 is, therefore, a highfrequency signal similar to the test stimuli signals but at levelsdetermined by the quality of the device under test.

It will be appreciated that a typical DUT 14 may produce several outputsignals in response to one or more test stimuli, and because of the veryhigh frequency of the signals and the various propagation delays throughthe various circuits, it is probable that the several output signalswill not be properly aligned with each other when returned to thecomputer 12. Therefore, the output of the comparator 30 is applied to askew adjustment circuit 36, as shown in FIG. 4. It will be noted thatthe circuit 36 of FIG. 4 is identical with the coarse and fine skewadjustment circuit 22 of FIG. 2; it is therefore deemed unnecessary todescribe this circuit 36 in detail.

The output of the skew adjusting circuit 36 is then buffered with an ECLgate 180 and applied back to the computer through terminals 182 for aquality determination of the device under test.

We claim: .[.
 1. A high-speed testing circuit for applying test stimuliinput signals to an electronic device and for receiving from said deviceoutput signals generated in response to test stimuli signals originatingfrom another source, said testing circuit including:a. voltage referencecircuitry for supplying a pair of D.C. signals at first and secondvoltage levels, said circuitry including input means for receiving D.C.signals at first, second, third, and fourth voltage levels and means forselecting appropriate first and second levels for testing the electronicdevice; b. skew adjustment circuit means for receiving a train of highfrequency pulses and for adjusting the time of occurrence of the leadingand trailing edges; c. driver circuit means coupled to receive from saidvoltage reference circuitry said pair of D.C. signals at first andsecond voltage levels and for receiving the adjusted train of pulsesfrom said skew adjustment circuit means, said driver circuit meansincluding electronic switching means for switching to said first and tosaid second voltage levels at a switching rate determined by thefrequency of said adjusted train of pulses to generate test stimulisignals for application to an input terminal of said electronicdevice..].
 2. The testing circuit claimed in claim .[.1.]. .Iadd.10.Iaddend.wherein said skew adjustment circuit means .[.includes coarseand.]. .Iadd.comprises: .Iaddend.fine skew adjustment means.[., saidfine adjustment means.]. comprising a variable resistor-capacitornetwork.[.,.]..Iadd.; .Iaddend.and .[.said.]. coarse .Iadd.skew.Iaddend.adjustment means comprising a gate circuit having apredetermined propagation delay, said gate circuit being selectivelyswitched into and out of said skew adjustment circuit means. .[.3. Thetesting circuit claimed in claim 1 wherein said driver circuit meansincludes: a. first and second diode bridge circuits, each having a firstterminal coupled to the interconnected anodes of said diodes, a secondterminal coupled to the interconnected cathodes and third and fourthterminals coupled between the cathode and anode of the diode pairsbetween said first and second terminals; b. output circuitry meansinterconnecting said fourth terminal of said first bridge circuit andsaid fourth terminal of said second bridge circuit with the outputconductor of said drive circuit means; c. current switching meanscoupled between a first voltage supply and said first terminal of saidfirst and second diode bridge circuits, and between a second voltagesupply and said second terminals of said first and second diode bridgecircuits, said current switching means coupled through common currentsource resistances to form a differential circuit through said first andsecond diode bridge circuits and said current switching means; d. inputcircuit means coupled to said voltage reference circuitry for applyingsaid D.C. signal at a first voltage level to the third terminal of saidfirst diode bridge and said D.C. signal at second voltage level to thethird terminal of said second diode bridge; and e. pulse input circuitmeans coupled to said skew adjustment circuit means and to said currentswitching means for switching current flow between said first and seconddiode bridge circuits at a rate determined by the frequency of said skewadjusted train of pulses..].
 4. The testing circuit claimed in claim.[.3.]. .Iadd.10 or 2 .Iaddend.wherein said pulse input circuit means.[.includes.]. .Iadd.comprises a .Iaddend.first and .Iadd.a.Iaddend.second signal .[.translators.]. .Iadd.translator .Iaddend.fortranslating the .[.pulse input signal voltage levels.]..Iadd.skew-adjusted pulses .Iaddend.into .Iadd.the intermediate pulsesat .Iaddend.levels required for operation of said current switchingmeans. The .[.circuitry.]. .Iadd.testing circuit .Iaddend.claimed inclaim 4 wherein each .[.of said first and second signal translatorscontain.]. .Iadd.signal translator comprises .Iaddend.a Zener diodecoupled between .[.resistances.]. .Iadd.resistors .Iaddend.between.[.said first and second.]. .Iadd.the .Iaddend.voltage supplies, the.[.resistances.]. .Iadd.resistors .Iaddend.and Zener diode in said first.Iadd.signal .Iaddend.translator being substantially identical with.[.resistances.]. .Iadd.the resistors .Iaddend.and .Iadd.Zener.Iaddend.diode in said second .Iadd.signal .Iaddend.translator to obtainsubstantially equal current flows through said .[.first and second.]..Iadd.signal .Iaddend.translators, .[.said pulse input signals.]..Iadd.the skew-adjusted pulses .Iaddend.being applied to .[.one side.]..Iadd.the anodes .Iaddend.of said Zener diodes and .[.signals to switchsaid current switching means taken from the opposite side.]. .Iadd.theintermediate pulses being produced at the cathodes .Iaddend.of said.Iadd.Zener .Iaddend.diodes at levels differing in voltage from the.[.level of said pulse input signals.]. .Iadd.levels of theskew-adjusted pulses .Iaddend.by the Zener voltage .[.rating.]. of said.Iadd.Zener .Iaddend.diodes.
 6. The .[.circuitry.]. .Iadd.testingcircuit .Iaddend.claimed in claim 4 wherein said .[.drive.]..Iadd.output .Iaddend.circuit means includes a high-speed.[.,normally-off.]. switch .[.in the output conductor of said drive circuitmeans, said switch.]. comprising at least one N-channel enhancement-typefield effect transistor having its gate coupled for switch conduction inresponse to applied input-output selection signals.
 7. The testingcircuit claimed in claim .[.1.]. .Iadd.10 or 2 and .Iaddend.furtherincluding comparator .[.circuitry coupled to receive.]. .Iadd.means forcomparing reference voltage signals with the device .Iaddend.outputsignals .[.from the electronic device under test.]., said comparator.[.circuitry including.]. .Iadd.means comprising .Iaddend.:.Iadd.a.Iaddend.first .[.and second comparators, said first.]. comparator for.[.receiving and.]. comparing first .Iadd.signals of the.Iaddend.reference voltage .[.levels.]. .Iadd.signals .Iaddend.with.Iadd.the device output .Iaddend.signals .[.from said electronicdevice,.]. .Iadd.to produce first compared signals; .Iaddend. .[.said.]..Iadd.a .Iaddend.second comparator for .[.receiving and.]. comparingsecond .Iadd.signals of the .Iaddend.reference voltage .[.levels.]..Iadd.signals .Iaddend.with .Iadd.the device output .Iaddend.signals.[.from said electronic device.]. .Iadd.to produce second comparedsignals.Iaddend.; and multiplexing .[.circuitry coupled to the outputsof said first and second comparators.]. .Iadd.means responsive to thefirst and second compared signals .Iaddend.and to the .[.output of saidskew adjustment circuit means for control by said adjusted train ofpulses.]. .Iadd.train of skew-adjusted pulses for generating comparatoroutput signals at a frequency corresponding to said switchingrate.Iaddend..
 8. The .Iadd.testing .Iaddend.circuit claimed in claim 7.Iadd.and .Iaddend.further including .[.a.]. delay .[.circuitinterposed.]. .Iadd.means coupled .Iaddend.between said.[.skew-adjustment.]. .Iadd.skew adjustment .Iaddend.circuit means andsaid multiplexing .[.circuitry.]. .Iadd.means .Iaddend.for.[.compensating.]. .Iadd.delaying the skew-adjusted pulses to compensate.Iaddend.for propagation delays .[.between pulses in said adjusted trainand the corresponding pulses received from said device.]. .Iadd.in saiddriver circuit means and in said comparator means.Iaddend..
 9. The.Iadd.testing .Iaddend.circuit claimed in claim 7 .Iadd.and.Iaddend.further including second skew adjustment circuit means.[.coupled to the output of said comparator circuitry, said adjustmentcircuit means having an adjustable fine skew adjustment means and aswitched coarse adjustment means.]. for compensating for propagationdelays between the comparator .[.circuitry.]. output signals and.Iadd.second comparator .Iaddend.output signals produced by otheridentical testing circuits operating in response to the .[.same teststimuli.]. .Iadd.device output .Iaddend.signals.Iadd., said second skewadjustment circuit means comprising:fine skew adjustment means; andcoarse skew adjustment means selectively switched into and out of saidsecond skew adjustment circuit means.Iaddend.. .Iadd.
 10. A high-speedtesting circuit for applying first test stimuli input signals to anelectronic device and for receiving device output signals from saiddevice generated in response to second test stimuli signals originatingfrom another source, said testing circuit comprising: voltage referencesupply circuit means for supplying a first direct current (D.C.)reference signal at a first voltage reference level and a second D.C.reference signal at a second voltage reference level in response to D.C.input signals at a plurality of input voltage levels; skew adjustmentcircuit means for receiving a train of high-frequency pulses and foradjusting the times of occurrences of the leading and trailing edges ofthe high-frequency pulses to produce a train of skew-adjusted pulses;and driver circuit means responsive to the D.C. reference signals and tothe train of skew-adjusted pulses for switching between the voltagereference levels at a switching rate determined by the frequency of thetrain of skew-adjusted pulses to generate the first test stimuli signalsfor application to an input terminal of said device, said driver circuitmeans comprising a. a first and a second diode bridge circuit, eachdiode bridge circuit comprising a first, a second, a third, and a fourthdiode and having (1) a first terminal coupled to the anodes of the firstand second diodes, (2) a second terminal coupled to the cathodes of thethird and fourth diodes, (3) a third terminal coupled between thecathode of the first diode and the anode of the third diode, and (4) afourth terminal coupled between the cathode of the second diode and theanode of the fourth diode; b. output circuit means coupled to the fourthterminals for transmitting the first test stimuli signals; c. currentswitching means for switching current between said diode bridge circuitsat said switching rate, said current switching means coupled between afirst voltage supply and the first terminals and coupled between asecond voltage supply and the second terminals, said current switchingmeans further coupled through common current-source resistors to form adifferential circuit through said diode bridge circuits; d. referenceinput circuit means coupled to said voltage reference supply circuitmeans for applying the first D.C. reference signal to the third terminalof said first diode bridge circuit and the second D.C. reference signalto the third terminal of said second diode bridge circuit; and e. pulseinput circuit means coupled to said skew adjustment circuit means forreceiving the train of skew-adjusted pulses and coupled to said currentswitching means for providing intermediate pulses thereto. .Iaddend.